Globally asynchronous locally synchronous wrapper circuit based on clock gating

In this paper we propose an asynchronous wrapper with new asynchronous communication port controllers and reliable clock generation scheme for locally synchronous modules. This is achieved by utilizing clock gating idea within GALS wrappers which makes the use of reliable and robust off-chip clock generator possible for locally synchronous modules. In addition to clock robustness, the clock generator part becomes totally synchronous. To validate the proposed solution, we employed the wrapper circuit in Viterbi error detection and correction circuit. The synthesis results show that our GALS approach gains 44%/spl sim/48% performance improvement in contrast to pausible clock GALS wrappers.