A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design

Author

Tachibana, Fumihiko ; Sato, Hironori ; Yamashita, Takahiro ; Hara, Hiroyuki ; Kitahara, Takeshi ; Nomura, Shuou ; Yamane, Fumiyuki ; Tsuboi, Yoshiro ; Seki, Keiko ; Matsumoto, Shuuji ; Watanabe, Yoshinori ; Hamada, Mototsugu

Author_Institution

Toshiba Corp., Kawasaki

fYear

2008

fDate

21-24 Sept. 2008

Firstpage

29

Lastpage

32

Abstract

A cell-based forward body-biasing technique to suppress the global process variation and its design flow are proposed. Latch-up free operation is guaranteed by embedded current source cells and limiter cells even when supply voltage is 1.2 V with small area overhead. By applying this technique to a media processor, the worst-case delay is reduced by 20% without sacrificing the maximum leakage spec.

Keywords

constant current sources; flip-flops; integrated circuit design; limiters; Latch-up free operation; cell-based forward body-biasing circuits; design flow; embedded current source cells; global process variation; limiter cells; media processor; voltage 1.2 V; Bipolar transistors; CMOS technology; Circuits; Delay; MOS devices; Microelectronics; Power dissipation; Threshold voltage; Variable structure systems; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-2018-6

Electronic_ISBN

978-1-4244-2019-3

Type

conf

DOI

10.1109/CICC.2008.4672012

Filename

4672012