Session 4 - High-speed test, characterization, and debug

Challenges associated with high speed I/O including cross-talk, channel characterization, ESD protection, and debug will be addressed in this session. Crosstalk affects circuit performance with three key variables: aggressor noise injection timing, aggressor location and direction, and voltage drop. The first paper provides an in-situ crosstalk delay measurement circuit and results on 65nm CMOS. As I/O data rates move to 10 Gb/s, the challenge of channel characterization is to understand the effect of die, packaging and board parasitics and their impact on signal integrity. This paper provides a test characterization methodology for separating out these effects for modeling. The benefits of inductive CDM ESD protection in 45nm planar CMOS technology is discussed in the third paper for an RF circuit operated at 13GHz. The session concludes with a tutorial overview of non-destructive optical beam failure analysis techniques for defect localization. Increasing IC complexities resulting from dense multi-level metallization and flip-chip packaging have left only the backside of the IC available for interrogation and which further complicates failure and yield analysis, especially in the presence of soft defects.