Regular routing architecture for a LUT-based MPGA

Mask programmable gate arrays (MPGAs) are an attractive solution to reduce design cost and turnaround time in ultra-deep submicron technologies. Several design methodologies have been proposed in the recent years for converting an evaluated field-programmable gate-array (FPGA) prototype design into an MPGA. In this paper, we investigate a predefined regular routing architecture of an MPGA. The routing architecture is easily scalable. A simple model for the MPGA interconnect is presented which facilitates static timing analysis. We explain the difference of this interconnect with the FPGA interconnect. The resulting MPGA is implemented in 130nm. Circuit level simulations show that our model is accurate in terms of delay. The study presents tradeoffs with the placement and routing to reach timing closure. A special MPGA routing tool is used. The study shows that high number of tracks in the MPGA is area prohibitive, but with better timing closure