Title :
A new multilevel hierarchical MFPGA and its suitable configuration tools
Author :
Marrakchi, Z. ; Mrabet , H. ; Mehrez, H.
Author_Institution :
Dept. ASIM-LIP6, Univ. Paris, France
Abstract :
In this paper we evaluate a new multilevel hierarchical MFPGA. The specific architecture includes two unidirectional programmable networks. A downward network based on the butterfly-fat-tree topology, and a special rising network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with fewer switches and a smaller area.
Keywords :
field programmable gate arrays; logic design; multivalued logic circuits; network routing; programmable circuits; trees (mathematics); Manhattan mesh architecture; butterfly-fat tree topology; multilevel hierarchical MFPGA; unidirectional programmable networks; Circuit topology; Field programmable gate arrays; Integrated circuit interconnections; Joining processes; Logic arrays; Network topology; Programmable logic arrays; Routing; Switches; Switching circuits;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.6
