DocumentCode :
3358933
Title :
NoC links energy reduction through link voltage scaling
Author :
Mineo, Andrea ; Palesi, Maurizio ; Ascia, Giuseppe ; Catania, Vincenzo
Author_Institution :
Univ. of Catania, Catania, Italy
fYear :
2013
fDate :
15-18 July 2013
Firstpage :
113
Lastpage :
120
Abstract :
The power dissipated by the links of a network-on-chip (NoC) accounts for a significant fraction of the overall power dissipated by the on-chip communication fabric. Such fraction becomes more relevant as technology shrinks. This paper presents a technique aimed at reducing the energy consumption of the NoC by means of link voltage swing reduction. The basic idea is run-time varying the link voltage swing based on the communication requirements in terms of reliability. Specifically, the voltage swing of the link is reduced when it has to transmit the flits of a packet belonging to a communication which admits a bit error rate higher than the usual. The experiments carried out on both synthetic and real traffic patterns show the effectiveness of the proposed technique which allows to save more than 20% of energy depending on the communications reliability requirements.
Keywords :
energy consumption; integrated circuit reliability; network-on-chip; power aware computing; NoC link energy reduction; communications reliability requirements; energy consumption; link voltage scaling; link voltage swing reduction; network-on-chip; on-chip communication fabric; real traffic patterns; synthetic traffic pattern; Bit error rate; Crosstalk; Energy consumption; Quality of service; Robustness; Transceivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013 International Conference on
Conference_Location :
Agios Konstantinos
Type :
conf
DOI :
10.1109/SAMOS.2013.6621113
Filename :
6621113
Link To Document :
بازگشت