Exploiting software pipelining for network-on-chip architectures

Recent developments in process technology have made it possible to produce chips consisting of a large number of processing elements. For factors such as scalability, performance, power-efficiency, the interconnection structure supporting such a chip needs to be an on-chip network architecture rather than a conventional bus-based system. Recent research has studied such network-on-chip (NoC) based systems from the performance and throughput, power/energy, reliability, predictability, synchronization, and concurrency perspectives. However, most of these studies are hardware based and it is not clear what type of compiler support would be best suited for these NoC based systems. Focusing on a mesh based NoC architecture that connects multiple processor cores, this paper explores the effectiveness of voltage/frequency scaling for processors and communication links with and without software pipelining, a compiler optimization for increasing parallelism. To our knowledge, this is the first paper that explores the influence of software pipelining in the context of the embedded NoC architectures