Title :
Optimisation of the SHA-2 family of hash functions on FPGAs
Author :
McEvoy, R.P. ; Crowe, F.M. ; Murphy, C.C. ; Marnane, W.P.
Author_Institution :
Dept. of Electr. & Electron. Eng., Cork Univ. Coll.
Abstract :
Hash functions play an important role in modern cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby allowing rapid prototyping of several designs. Speed/area results from these processors are analysed and are shown to compare favourably with other FPGA-based implementations, achieving the fastest data throughputs in the literature to date
Keywords :
VLSI; cryptography; field programmable gate arrays; logic design; microprocessor chips; optimisation; pipeline processing; FPGA; SHA-256; SHA-512; VLSI architecture; cryptography; hardware optimisation techniques; hash functions; rapid prototyping; Cryptographic protocols; Cryptography; Data security; Field programmable gate arrays; Hardware; Internet; NIST; Prototypes; Transport protocols; Very large scale integration;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.70
