CHESS: a comprehensive tool for CDFG extraction and synthesis of low power designs from VHDL

In this paper, a new tool CHESS, is designed and developed for control and data-flow graph (CDFG) extraction and the high level synthesis of low power designs from behavioral level VHDL descriptions. The tool optimizes latency, area and power during the different phases of synthesis and provides several solutions to evaluate the trade-offs during design. Unlike the case of DFGs, not much work has been reported in the literature for low power synthesis of CDFGs. The tool consists of three individual modules: (i) CDFG extraction, (ii) scheduling and allocation of the CDFG, and (iii) binding, which are integrated to form a comprehensive high-level synthesis system. The first module for CDFG extraction includes a new algorithm in which compiler-level transformations are applied, followed by a series of behavioral-preserving transformations on the given VHDL description. The CDFG is fed to the scheduling module for resource optimization under the given set of time constraints. The scheduling algorithm is an improvement over the tabu search based algorithm described in (Amellal and Kaminska, 1994) in terms of execution time. The improvement is achieved by pre-identification of mutually exclusive operations in the CDFG extraction phase, which, otherwise, is normally done during scheduling. The third and the final module of the proposed tool implements a new binding algorithm based on a game-theoretic formulation. The problem of binding is formulated as a noncooperative finite normal game, and Nash equilibrium function is applied to achieve a power-optimized binding solution. Experimental results for several high-level synthesis benchmarks are presented which establish the efficacy of the proposed synthesis tool