Ultra-low energy computing with noise: Energy performance probability

Noise susceptibility and power density have become two limiting factors to CMOS technology scaling. As a solution to these challenges, probabilistic CMOS (PCMOS) based computing has been proposed. PCMOS devices are inherently probabilistic devices that compute correctly with a probability p. This paper investigates the trade-offs between the energy, performance and probability of correctness (p) of a PCMOS inverter. Using simple analytical models of energy, delay and p of a PCMOS inverter, the optimum energy delay product (EDP) value for given probability and performance constraints is found. The analytical models are validated using circuit simulations for a PCMOS inverter designed in a 0.13μm process. The results show that operating the PCMOS inverter at lower supply voltages is more preferable in terms of minimizing EDP. Our analysis is useful in optimal (in terms of EDP) circuit design for satisfying application requirements in terms of performance and probability of correctness. An analysis of the impacts of the variations in the temperature and the threshold voltage on the optimal EDP values is also included.