Routing-tree construction with concurrent performance, power and congestion optimization

Author

Alkan, C. ; Chen, T.

Author_Institution

Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO

fYear

2006

fDate

2-3 March 2006

Abstract

We present a routing-tree construction algorithm that considers multi-objectives of performance, power and congestion concurrently. Congestion is measured with balanced usage of routing resources among layers. Simultaneous buffer insertion and layer assignment tends to produce routing-trees with shorter overall length. Applying the proposed simultaneous algorithm on a subset of routes on a commercial 64-bit microprocessor yielded 9% less repeater usage and 1.5% shorter overall routing-tree length with improved overall performance at the same time, compared to sequential routing-tree construction approach

Keywords

buffer circuits; circuit complexity; microprocessor chips; network routing; trees (mathematics); 64 bit; buffer insertion; congestion optimization; layer assignment; microprocessors; power optimization; routing resources; sequential routing tree construction; Concurrent computing; Costs; Delay; Power engineering and energy; Power engineering computing; Routing; Timing; Topology; Very large scale integration; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on

Conference_Location

Karlsruhe

Print_ISBN

0-7695-2533-4

Type

conf

DOI

10.1109/ISVLSI.2006.80

Filename

1602466