A 16b 10MS/s digitally self-calibrated ADC with time constant control

Time constant control (TCC) incorporating on-chip digital self-calibration technique performs two-step calibration of pipeline ADC stage errors and reduces power consumption at the same time. Using the proposed technique, the current of the amplifier in 1^st pipeline stage employing TCC is reduced by 93%. The prototype 3.3 V 16 b 10 MS/s ADC based on 65 nm CMOS process is implemented in an active die area of 1.32 mm² and the on-chip calibration logic occupies only 18% of the die area. The reduction of overall power consumption of the ADC is 36%, from 123.8 mW to 79.2 mW with TCC. After TCC and digital self-calibration, the measured DNL, INL, and SNDR are plusmn0.65 LSB, plusmn5.76 LSB, and 75.4 dB, respectively, for a 5 MHz and 2.4 Vpp differential input signal at 10 MS/s.