Special session on “Fault-tolerant techniques for computer systems, architectures and processors”

As semiconductor technology scales, chips are becoming ever less reliable; prominent reasons for this phenomenon are the sheer number of transistors on a given silicon area and their shrinking device features. As a consequence, reliability is an increasing concern not only for safety-critical systems, but also for many other application domains in Embedded systems. However, traditional solutions for fault tolerance, e.g. provided through various redundancy schemes, have disproportionally increasing power and performance costs. This, in turn, limits substantially systems´ efficiency, especially due to the fact that performance scaling and power are becoming significant design challenges, too. In the face of such changes in the technological landscape, this special session offers original contributions for fault-tolerant computer systems, architectures and processors, which address the above challenges.