DocumentCode
3359214
Title
A High Speed Reduced Pin Count JTAG Interface
Author
Whetsel, Lee
Author_Institution
Texas Instruments. l-whetsel@ti.com
fYear
2006
fDate
Oct. 2006
Firstpage
1
Lastpage
10
Abstract
This paper describes a high speed reduced pin count JTAG interface between a JTAG controller and target IC. Being able to access JTAG using only one or two pins allows JTAG to be designed into ICs that in the past have been resistant to JTAG, such as JEDEC standard package memories, microcontrollers, and mixed signal devices
Keywords
high-speed integrated circuits; integrated circuit testing; integrated memory circuits; mixed analogue-digital integrated circuits; JEDEC standard package memories; JTAG controller; JTAG interface; high speed interface; microcontrollers; mixed signal device; reduced pin count; target integrated circuit; Bandwidth; Bidirectional control; Circuit testing; Clocks; Communication system control; High speed integrated circuits; Instruments; Performance evaluation; Transceivers; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2006. ITC '06. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
1-4244-0292-1
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2006.297619
Filename
4079297
Link To Document