A low-power 2D bypassing multiplier using 0.35 μm CMOS technology

This paper presents a low power 8 × 8 digital multiplier designs by taking advantage of a 2D bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Hence, it is a 2D bypassing architecture. Thorough post-layout simulations show that the power dissipation of the proposed design is reduced by more than 75% compared to the prior design with obscure cost of delay and area. A physical implementation of the proposed design using a standard 0.35 μm 2P4M CMOS process is also presented to justify the functionality as well as the low power performance of the 2D bypassing method.