Title :
An optimized BIST architecture for FPGA look-up table testing
Author :
Yarandi, M.S. ; Alaghi, A. ; Navabi, Z.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Abstract :
This paper presents a complete BIST architecture for FPGA look-up tables. This architecture can detect multiple faults, and can be configured to detect a fault in as few as five LUTs. Unlike an earlier work, our method places the output response analyzer (ORA) within the FPGA.
Keywords :
built-in self test; fault diagnosis; field programmable gate arrays; logic testing; network analysers; table lookup; BIST architecture; FPGA; fault detection; look-up table testing; multiple faults; output response analyzer; Built-in self-test; Circuit faults; Circuit testing; Clocks; Computer architecture; Fault detection; Field programmable gate arrays; Personal communication networks; Space vector pulse width modulation; Table lookup;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.24
