Title :
Highly reliable W/TiN/pn-poly-Si gate CMOS technology with simultaneous gate and source/drain doping process
Author :
Wakabayashi, H. ; Andoh, T. ; Sato, T. ; Yoshida, T. ; Miyamoto, T. ; Mogami, T. ; Kunio, T.
Author_Institution :
Microelectron. Res. Labs., NEC Corp., Kanagawa, Japan
Abstract :
A novel W/TiN/pn-poly-Si gate structure has been developed for merged memory and logic LSIs by using sub-quarter micron pn-poly-Si gate CMOS devices. Low-resistance and thermally stable tungsten (W) films were obtained by 5-nm titanium nitride (TiN) film between tungsten film and poly-Si film. This W/TiN/poly-Si gate electrode has a good heat resistance after RTA process at 1000/spl deg/C for 10 seconds. 0.22-/spl mu/m W/TiN/pn-poly-Si gate CMOS devices without interdiffusion through the gate electrode were fabricated by using a simultaneous gate and source/drain (SD) doping process.
Keywords :
CMOS digital integrated circuits; integrated circuit metallisation; integrated circuit reliability; ion implantation; rapid thermal annealing; thermal stability; titanium compounds; tungsten; 0.22 mum; 10 s; 1000 C; 5 nm; RTA process; W-TiN-Si; W/TiN/pn-poly-Si gate CMOS technology; gate doping; heat resistance; high reliability; interdiffusion suppression; ion implantation; low sheet resistance; low-resistance thermally stable W films; merged memory/logic LSIs; source/drain doping process; sub-quarter micron pn-poly-Si gate CMOS devices; thermal stability; CMOS logic circuits; CMOS process; CMOS technology; Doping; Electrodes; Logic devices; Resistance heating; Tin; Titanium; Tungsten;
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3393-4
DOI :
10.1109/IEDM.1996.553623
