A flexible architecture for block turbo decoders using BCH or Reed-Solomon components codes

Author

Piriou, E. ; Jego, C. ; Adde, P. ; Jezequel, M.

Author_Institution

CNRS TAMCIC UMR, Brest

fYear

2006

fDate

2-3 March 2006

Abstract

In this paper, the first flexible architecture dedicated to block turbo decoders is presented The major innovation concerns the component code that is used by the block turbo code. In fact, our architecture is able to decode BCH and Reed-Solomon codes with single or double correction power. To the authors´ knowledge, this is the first architecture implementing Reed-Solomon block turbo codes. This approach makes it possible to select the block turbo decoder architecture using optimum component codes in any circumstance. Our flexible elementary SISO decoder is dedicated to extended binary BCH codes (32,26) and (32,21) and to nonextended Reed-Solomon codes (31,29) and (31,27). Experimentation has been done on a Stratix-based NIOS development board

Keywords

BCH codes; Reed-Solomon codes; binary codes; block codes; decoding; turbo codes; BCH components codes; Reed-Solomon components codes; Stratix-based NIOS development board; binary BCH codes; block turbo decoders; elementary SISO decoder; flexible SISO decoder; flexible architecture; optimum component codes; Concatenated codes; Digital communication; Error correction codes; Iterative decoding; Parity check codes; Power engineering and energy; Product codes; Reed-Solomon codes; Technological innovation; Turbo codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on

Conference_Location

Karlsruhe

Print_ISBN

0-7695-2533-4

Type

conf

DOI

10.1109/ISVLSI.2006.2

Filename

1602481