A high-capacity broadband packet switch architecture based on multilink approach

The authors present a design for a broadband packet switch that uses multiple links in parallel to realize a high-speed channel. This implementation permits the switch to operate at the link rate, e.g. at 150 Mb/s, while having the ability to support a channel at higher rates, e.g. at 2.4 Gb/s. The main contribution of the design is that packet sequence on a channel is maintained even though packets are allowed to use any of the links belonging to the same channel. Besides allowing the switch to function at a slower rate than the transmission channel rate, the implementation of the multilinks benefits from statistical multiplexing gain