DocumentCode
3359500
Title
A robust synchronizer
Author
Jun Zhou ; Kinniment, D. ; Russell, G. ; Yakovlev, A.
Author_Institution
Newcastle Univ.
fYear
2006
fDate
2-3 March 2006
Abstract
We describe a new latch circuit designed to give a high performance in low voltage synchronizer applications. By increasing the latch current only during metastability, we can more than maintain the value of the metastability time constant, tau without significantly increasing the power. Our circuit also reduces the variation of tau with Vdd and temperature, so that it has a lower tau at 50% Vdd than the conventional jamb latch has at 60% Vdd
Keywords
circuit stability; flip-flops; low-power electronics; synchronisation; latch circuit; latch current; low voltage synchronizer; metastability time; robust synchronizer; Capacitance; Circuits; Clocks; Latches; Metastasis; Power supplies; Robustness; Synchronization; Temperature; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location
Karlsruhe
Print_ISBN
0-7695-2533-4
Type
conf
DOI
10.1109/ISVLSI.2006.12
Filename
1602487
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