• DocumentCode
    3359536
  • Title

    The Challenge of Testing the ARM CORTEX-A8/sup TM/ Microprocessor Core

  • Author

    McLaurin, Teresa L.

  • Author_Institution
    ARM Inc., Austin, TX
  • fYear
    2006
  • fDate
    22-27 Oct. 2006
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    The DFT and test challenges faced, and the solutions applied, to the Cortex-A8 microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT core solution that ultimately end up in many different environments. This core comprises synthesized, hand-mapped, hand-placed (HMHP) and custom blocks. A DFT solution had to be created that could be utilized by a multitude of customers
  • Keywords
    design for testability; logic testing; microprocessor chips; Cortex-A8 microprocessor core; DFT core solution; DFT techniques; custom blocks; design for testability; hand-mapped blocks; hand-placed blocks; synthesized blocks; Clocks; Design for testability; Error correction codes; Frequency; Logic design; Logic testing; Microprocessors; Pipelines; Registers; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2006. ITC '06. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    1-4244-0291-3
  • Electronic_ISBN
    1089-3539
  • Type

    conf

  • DOI
    10.1109/TEST.2006.297638
  • Filename
    4079316