DocumentCode :
3359741
Title :
Faster statistical cell characterization using adjoint sensitivity analysis
Author :
Gu, Ben ; Gullapalli, Kiran ; Zhang, Yun ; Sundareswaran, Savithri
Author_Institution :
Design Technol. Organ., Freescale Semicond., Austin, TX
fYear :
2008
fDate :
21-24 Sept. 2008
Firstpage :
229
Lastpage :
232
Abstract :
With the adoption of statistical static timing analysis (SSTA), the characterization of standard cell libraries for delay variations and output transition time (output slew) variations, referred to as statistical characterization, is becoming essential. Statistical characterization of intra-cell mismatch variations as well as inter-chip variations need to be performed efficiently with acceptable accuracy as a function of process parameter variations. The conventional approach to this problem is to model these mismatch variations by characterizing each device variation separately. However, this entails a cost that is proportional to the product of the number of devices (nd) in the cell and the number of local statistical parameters (np), and characterization becomes infeasible. In this work, we propose an improved transient sensitivity analysis to accelerate statistical characterization. We compute sensitivities of node voltages with respect to any process/design parameters. These sensitivities are used to extract the sensitivities of delays and transition times. It is more critical to note the sparsity of the circuitpsilas dependence on the statistical parameters (i.e., any given parameter directly impacts only a small portion of the circuit, sometimes only one device). By exploiting this sparsity we obtain a method that is O(np), compared to O(nptimesnd ) of the conventional approach. As an example, for an AOI cell with 40 devices, the sensitivity analysis, compared to the standard approach using multiple simulations, results in more than 18X runtime improvements with better accuracy.
Keywords :
delays; integrated circuit design; statistical analysis; adjoint sensitivity analysis; delay variations; intracell mismatch variations; local statistical parameters; standard cell libraries; statistical cell characterization; statistical static timing analysis; transient sensitivity analysis; Acceleration; Circuits; Costs; Delay effects; Libraries; Process design; Sensitivity analysis; Timing; Transient analysis; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
Type :
conf
DOI :
10.1109/CICC.2008.4672065
Filename :
4672065
Link To Document :
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