Title :
Configurational Workload Characterization
Author :
Najaf-Abadi, Hashem H. ; Rotenberg, Eric
Author_Institution :
NC State Univ., Raleigh, NC
Abstract :
Although the best processor design for executing a specific workload does depend on the characteristics of the workload, it can not be determined without factoring-in the effect of the interdependencies between different architectural subcomponents. Consequently, workload characteristics alone do not provide accurate indication of which workloads can perform close-to-optimal on the same architectural configuration. The primary goal of this paper is to demonstrate that, in the design of a heterogeneous CMP, reducing the set of essential benchmarks based on relative similarity in raw workload behavior may direct the design process towards options that result in sub-optimality of the ultimate design. It is shown that the design parameters of the customized processor configurations, what we refer to as the configurational characteristics, can yield a more accurate indication of the best way to partition the workload space for the cores of a heterogeneous system to be customized to. In order to automate the extraction of the configurational- characteristics of workloads, a design exploration tool based on the Simplescalar timing simulator and the CACTI modeling tool is presented. Results from this tool are used to display how a systematic methodology can be employed to determine the optimal set of core configurations for a heterogeneous CMP under different design objectives. In addition, it is shown that reducing the set of workloads based on even a single widely documented benchmark similarity (between bzip and gzip) can lead to a slowdown in the overall performance of a heterogeneous-CMP design.
Keywords :
microprocessor chips; CACTI modeling tool; Simplescalar timing simulator; architectural configuration; configurational workload characterization; design exploration tool; heterogeneous system; Art; Clocks; Computer architecture; Costs; Displays; Microarchitecture; Process design; Reduced instruction set computing; Timing; VLIW; C.1.1 [Single Data Stream Architectures]: RISC/CISC; Single-instruction-stream; VLIW architectures; customization; design exploration; heterogeneous CMP; single-thread performance; workload characterization;
Conference_Titel :
Performance Analysis of Systems and software, 2008. ISPASS 2008. IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-2232-6
Electronic_ISBN :
978-1-4244-2233-3
DOI :
10.1109/ISPASS.2008.4510747