Title :
Efficient Latch and Clock Structures for System-on-Chip Test Flexibility
Author :
Lackey, David E.
Author_Institution :
Microelectron. Div., IBM, Essex Junction, VA
Abstract :
This paper describes a novel implementation of edge-triggered flip-flops that incorporates the most optimum features of the leading design-for-testability (DFT) methods in the industry in a manner that is efficient from the standpoint of performance, power and area. The result is a flip-flop design that provides testability that is free of timing hazards (race-free and LSSD compatible), while operating at product frequency using only a single edge clock
Keywords :
design for testability; flip-flops; integrated circuit testing; system-on-chip; DFT; clock structure; design-for-testability methods; edge-triggered flip-flops; latch structure; single edge clock; system-on-chip test flexibility; Circuit testing; Clocks; Design for testability; Flip-flops; Latches; Logic testing; Master-slave; System testing; System-on-a-chip; Timing;
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
1-4244-0292-1
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2006.297657
