DocumentCode :
3360031
Title :
Test Data Compression of 100x for Scan-Based BIST
Author :
Arai, Masayuki ; Fukumoto, Satoshi ; Iwasaki, Kazuhiko ; Matsuo, Tatsuru ; Hiraide, Takahisa ; Konishi, Hideaki ; Emori, Michiaki ; Aikyo, Takashi
Author_Institution :
Tokyo Metropolitan Univ.
fYear :
2006
fDate :
Oct. 2006
Firstpage :
1
Lastpage :
10
Abstract :
The authors have developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. The scheme achieved a 100times compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, the masking logic was enhanced to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. The scheme was applied to five real VLSI chips, and the technique compressed the test data by 100times for scan-based BIST
Keywords :
VLSI; automatic test pattern generation; built-in self test; data compression; integrated circuit testing; ATPG vectors; LFSR pre-shifting; X-masking; built in self test; invert-and-shift operation; masking logic; run-length compression; scan BIST; scan address partitioning; test data compression; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Costs; Logic testing; Test data compression; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
ISSN :
1089-3539
Print_ISBN :
1-4244-0292-1
Electronic_ISBN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2006.297664
Filename :
4079342
Link To Document :
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