DocumentCode :
3360128
Title :
Multi-Gigahertz Testing of Wafer-Level Packaged Devices
Author :
Majid, A.M. ; Keezer, D.C. ; Jayabalan, J. ; Rotaru, M.R.
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA
fYear :
2006
fDate :
Oct. 2006
Firstpage :
1
Lastpage :
10
Abstract :
The authors are developing alternative approaches for wafer-level packaging (WLP) of high-performance, high I/O-density chips. The electrical contacts are patterned onto the wafer surface using lithographic processes in order to provide high density I/Os at a very low cost per pin. In order to fully exploit these new packaging technologies, a compatible testing approach is also needed. This paper describes one of the WLP I/O structures, a new bare-die test socket, and a low-cost multi-GHz miniature tester. Our initial objective for this WLP technology is 5 Gbps; and the operation of interconnects, the bare-die test socket, and the miniature tester at this rate and slightly higher (6.4 Gbps), was demonstrated. The miniature tester alone is demonstrated up to 8 Gbps
Keywords :
integrated circuit testing; lithography; test equipment; wafer level packaging; 5 Gbit/s; 8 Gbit/s; bare-die test socket; electrical contacts; high I/O-density chips; lithographic processes; multi-gigahertz testing; wafer-level packaged devices; Built-in self-test; Chip scale packaging; Contacts; Costs; Electronics packaging; Field programmable gate arrays; Integrated circuit packaging; Sockets; Testing; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
ISSN :
1089-3539
Print_ISBN :
1-4244-0292-1
Electronic_ISBN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2006.297669
Filename :
4079347
Link To Document :
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