Title :
Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs
Author :
Sakimura, Noboru ; Sugibayashi, Tadahiko ; Nebashi, Ryusuke ; Kasai, Naoki
Author_Institution :
Device Platforms Labs., NEC Corp., Sagamihara
Abstract :
A nonvolatile magnetic flip-flop (MFF) primitive cell for SoC design libraries has been developed using a unique MRAM process. It has high design compatibility with conventional CMOS LSI designs. MFF maximum frequency was estimated to be 3.5 GHz, which is comparable to that of a normal CMOS DFF. An MFF test chip was fabricated with the process. The chippsilas functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of SoCs dramatically.
Keywords :
CMOS integrated circuits; MRAM devices; flip-flops; system-on-chip; CMOS LSI designs; MRAM process; SoC design libraries; nonvolatile magnetic flip-flop; power dissipation; primitive MFF cell; CMOS process; Circuits; Clocks; Energy consumption; Flip-flops; Large scale integration; Latches; Magnetic separation; Magnetic tunneling; Magnetization;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672095
