Title :
Tessellation-enabled shader for a bandwidth-limited 3D graphics engine
Author :
Chung, Kyusik ; Yu, Chang-Hyo ; Kim, Donghyun ; Kim, Lee-Sup
Author_Institution :
Dept. of EECS, KAIST, Daejeon
Abstract :
A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. By utilizing operational characteristic of tessellation, the TES is implemented with 6.2% additional logic of a dedicated unit based on a conventional vertex shader. With optimization of key components of a shader, a symmetric dual-core TES is fabricated using 0.18 um CMOS technology and processes 120 Mvertices/s at 100 MHz while consuming 272 mW of power.
Keywords :
CMOS logic circuits; computer graphic equipment; low-power electronics; multimedia systems; system-on-chip; CMOS technology; bandwidth-limited mobile 3D graphics engine; mobile multimedia SoC; power 272 mW; power consumption; size 0.18 mum; symmetric dual-core TES; tessellation-enabled shader; Bandwidth; CMOS logic circuits; CMOS process; CMOS technology; Engines; Geometry; Graphics; Logic arrays; Multimedia systems; System-on-a-chip;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672098
