DocumentCode :
3360559
Title :
Multilevel reverse-carry computation for comparison and for sign and overflow detection in addition
Author :
Lang, Tomas ; Bruguera, Javier D.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
fYear :
1999
fDate :
1999
Firstpage :
73
Lastpage :
79
Abstract :
A fast calculation of the most-significant carry in an addition is required in several applications, such as comparisons of two operands by performing their difference, sign detection, and overflow detection. It has been proposed to calculate this carry by detecting the most-significant carry chain and collecting the carry after this chain. The detection can be implemented by a prefix tree of AND gates and the collecting by a multi-input OR or by a connection with tristate buffers. We have performed an estimate of the delay of this implementation for a datapath width of 64 bits and conclude that it is not significantly faster than the traditional carry-lookahead based method. We propose a multilevel implementation, which allows the overlap of successive levels thereby reducing the overall delay. For 64-bit operands we estimate a delay reduction of about 15% with respect to the traditional carry-lookahead based method, with a similar number of gates and number and length of interconnections
Keywords :
carry logic; logic design; AND gates; addition; carry-lookahead based method; delay reduction; interconnections; most-significant carry; multilevel implementation; multilevel reverse-carry computation; overflow detection; sign detection; tristate buffers; Application software; Contracts; Delay estimation; Energy consumption; Hardware;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 1999. (ICCD '99) International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-7695-0406-X
Type :
conf
DOI :
10.1109/ICCD.1999.808390
Filename :
808390
Link To Document :
بازگشت