Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines

A configurable replica bitline (cRBL) technique for controlling sense-amplifier enable (SAE) timing for small-swing bitline SRAMs is described. Post-silicon selection of a subset of replica bitline driver cells from a statistically designed pool of cells facilitates precise SAE timing. An exponential reduction in timing variation is enabled by statistical selection of driver cells, which can provide 14x reduction in SAE timing uncertainty with 200x less area and power than a conventional RBL with equivalent variation control. We describe the post-silicon test and configuration methodology necessary for cRBLs. To demonstrate the efficacy of the proposed cRBL technique, we present measured results from a 90 nm bulk CMOS 64 kb SRAM testchip.