Title :
A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology
Author :
Hwang, Myeong-Eun ; Roy, Kaushik
Author_Institution :
Purdue Univ., West Lafayette, IN
Abstract :
Cell stability and tolerance to process variation are of primary importance in subthreshold SRAMs. We propose a DTMOS based 6T SRAM suitable for subthreshold operation. For variation tolerant memory peripheral circuitry, we apply beta-ratio modulation technique. DTMOS SRAM array fabricated in 90 nm technology operates down to 135 mV consuming 0.13 muW at 750 Hz. The proposed SRAM achieves 200% improvement in read static noise margin at iso-area compared to the conventional 6T SRAM at a supply voltage of 200 mV.
Keywords :
MOS memory circuits; SRAM chips; circuit stability; DTMOS SRAM array; cell stability; dynamic threshold MOS; frequency 750 Hz; memory peripheral circuitry; power 0.13 muW; process variation; ratio modulation; size 90 nm; static noise; subthreshold SRAM; voltage 135 mV; voltage 200 mV; Application software; Circuit noise; Circuit stability; Dynamic voltage scaling; Inverters; Logic devices; Personal digital assistants; Portable computers; Random access memory; Threshold voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672109