Signal/power integrity design strategy for low-cost package of high-speed memory I/O interfaces

Based on the characteristic current on the stub series terminated logic (SSTL) topology, three design parameters, the effective power and ground inductance and the signal loop inductance, are proposed to evaluate on the performance of signal integrity (SI) and power integrity (PI) for the memory circuits. From these three parameters, a design flow systematically describes how to design the layout of package for the designers is presented. Using this design flow, an improved package, which refines from a real package substrate, are shown to have better performance of SI and PI under the condition of identical layout area. Finally, the chip-package co-simulation at time domain verified the validity of the design ideas.