DocumentCode
3360644
Title
A million cycle 0.13um 1Mb embedded SONOS Flash memory using Successive Approximated Read Calibration
Author
Wang, N. ; Yao, X. ; Lei, Y. ; Feng, G.Y. ; Dong, Q.H. ; Xu, L. ; Guo, L. ; Wang, Z. ; Tang, T.S.
Author_Institution
Shanghai Hua Hong NEC Electron. Co., Ltd., Shanghai
fYear
2008
fDate
21-24 Sept. 2008
Firstpage
427
Lastpage
430
Abstract
A 1 Mb embedded 2T-SONOS Flash macro is implemented in 0.13 um logic compatible process. The Flash macro has improved reliability and yield with a power-on Successive Approximated Read Calibration (SARC). Word-line decoder area is greatly reduced using 1.8 V transistors to tolerate high voltage. Source degenerated compensation is implemented to enhance read margin. The Flash macro consumes 1.0 mA at 50 ns 1.8 V access and 0.5 uA in standby mode, and achieves one million cycling and 20-year data retention.
Keywords
CMOS memory circuits; embedded systems; flash memories; SARC; embedded SONOS flash memory; flash macro reliability; size 0.13 mum; source degenerated compensation; storage capacity 1 Mbit; successive approximated read calibration; word-line decoder area; Calibration; Decoding; Driver circuits; Flash memory; Logic; National electric code; SONOS devices; Smart cards; Temperature sensors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-2018-6
Electronic_ISBN
978-1-4244-2019-3
Type
conf
DOI
10.1109/CICC.2008.4672111
Filename
4672111
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