A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI

An all static CMOS (45 nm SOI) all-digital fractional-N PLL has a wide tuning range (from 0.84 GHz to 13.3 GHz, at 1.0 V, 65degC) and supports a broad range of multiplication factors (up to 1,000x) and reference clock speeds (from 2 MHz to 1 GHz). At 125degC the period jitter of the 4.12 GHz clock (206 MHz reference) is 1.1 ps rms (11.4 ps pp) at 1.3 V (52.4 mW), and 2.2 ps rms, (22.7 ps pp) at 0.7 V (9.7 mW). The area of the PLL is 175 mum times 160 mum.