ASAP-a 2D DFT VLSI processor and architecture

Author

Mellott, Jonathon D. ; Lewis, Michael ; Taylor, Fred ; Coffield, P.

Author_Institution

Florida Univ., Gainesville, FL, USA

Volume

2

fYear

1996

fDate

12-15 May 1996

Firstpage

261

Abstract

In this paper we examine the use of a recent innovation, called the logarithmic residue number system or LRNS, as an alternative to conventional DSP processors for implementing multiply-accumulate (MAC) operations. ASAP is a custom VLSI multiprocessor chip based on the LRNS. The fabricated ASAP device is capable of achieving MAC bandwidth-area ratios far greater than a conventional processor. The architecture of the ASAP device is discussed in detail as well as its application to the FFT

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; discrete Fourier transforms; fast Fourier transforms; residue number systems; systolic arrays; 2D DFT VLSI processor; ASAP; DSP chip; FFT; LRNS; MAC bandwidth-area ratios; VLSI architecture; custom VLSI multiprocessor chip; logarithmic RNS; logarithmic residue number system; multiply-accumulate operations; Adders; Arithmetic; Computer architecture; Digital signal processing chips; Power dissipation; Power system reliability; Signal processing; Technological innovation; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.540402

Filename

540402