DocumentCode :
3360728
Title :
A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of −28dB
Author :
Arakali, Abhijith ; Gondi, Srikanth ; Hanumolu, Pavan Kumar
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR
fYear :
2008
fDate :
21-24 Sept. 2008
Firstpage :
443
Lastpage :
446
Abstract :
A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. The prototype PLL, incorporating a novel regulator, is fabricated in a 0.18 mum digital CMOS process and operates from 0.5 to 2.5 GHz. At 1.5 GHz, the proposed PLL achieves a worst-case noise sensitivity of -28 dB (0.5 rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.
Keywords :
CMOS integrated circuits; integrated circuit noise; phase locked loops; sensitivity analysis; PLL; current 2.2 mA; digital CMOS process; frequency 0.5 GHz to 2.5 GHz; noise figure 20 dB; noise sensitivity; power consumption; supply-noise rejection performance; supply-regulated phase-locked loop; voltage 1.8 V; worst-case noise sensitivity; Bandwidth; Clocks; Energy consumption; Integrated circuit noise; Noise generators; Phase locked loops; Power dissipation; Regulators; Voltage control; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
Type :
conf
DOI :
10.1109/CICC.2008.4672116
Filename :
4672116
Link To Document :
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