A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of −28dB

A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. The prototype PLL, incorporating a novel regulator, is fabricated in a 0.18 mum digital CMOS process and operates from 0.5 to 2.5 GHz. At 1.5 GHz, the proposed PLL achieves a worst-case noise sensitivity of -28 dB (0.5 rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.