Title :
New high voltage SOI device structure eliminating substrate bias effects
Author :
Nakagawa, A. ; Yamaguchi, Y. ; Yasuhara, N. ; Hirayama, K. ; Funaki, H.
Author_Institution :
Toshiba Mater. & Devices Res. Lab., Kawasaki, Japan
Abstract :
The breakdown voltage of a conventional SOI device is limited because it requires a thicker buried oxide as well as a thicker silicon layer. A new SOI device structure and its substrate are proposed to break through these constraints. The proposed new SOI is characterized by a SIPOS (Semi-Insulating POly-crystalline Silicon) layer inserted between the silicon layer and the buried oxide. Since the SIPOS layer effectively shields the influence of the substrate bias, 600 V breakdown voltage SOI diodes and lateral IGBTs were successfully realized using a 0.8 /spl mu/m SIPOS layer and 0.8 /spl mu/m buried oxide.
Keywords :
buried layers; insulated gate bipolar transistors; power semiconductor diodes; semiconductor technology; silicon-on-insulator; 0.8 mum; 600 V; SIPOS layer; SOI diodes; Si-SiO/sub 2/; breakdown voltage; buried oxide thickness; high voltage SOI device structure; lateral IGBTs; substrate bias effects elimination; substrate bias shielding; Breakdown voltage; Crystallization; Diodes; Fabrication; Impurities; Insulated gate bipolar transistors; MOSFET circuits; Silicon; Surface resistance; Wafer bonding;
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3393-4
DOI :
10.1109/IEDM.1996.553630