Title :
A 33 V, 0.25 mΩ-cm2 n-channel LDMOS in a 0.65 μm smart power technology for 20-30 V applications
Author :
Parthasarathy, V. ; Zhu, R. ; Peterson, W. ; Zunino, M. ; Baird, R.
Author_Institution :
Motorola Inc., Mesa, AZ, USA
Abstract :
This paper describes a conventional 33 V n-channel lateral DMOS (LDMOS) transistor device integrated into a 20-30 V 0.65 μm (0.8 μm minimum feature size) smart power technology based on an analog BiCMOS process flow. A specific on-resistance of 0.25 mΩ-cm2 has been realized for this device without significantly compromising the performance of other devices in the technology. This is the lowest specific on-resistance obtained to date for a power device in this voltage range
Keywords :
BIMOS integrated circuits; electric resistance; integrated circuit testing; power MOSFET; power integrated circuits; 0.65 micron; 0.8 micron; 20 to 30 V; 33 V; analog BiCMOS process flow; minimum feature size; n-channel LDMOS; n-channel lateral DMOS transistor; power device voltage range; smart power technology; specific on-resistance; BiCMOS integrated circuits; Cutoff frequency; Degradation; Implants; Leakage current; MOS devices; Manufacturing processes; Surface resistance; Threshold voltage; Voltage control;
Conference_Titel :
Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-4752-8
DOI :
10.1109/ISPSD.1998.702629
