Title :
A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction
Author :
Agrawal, Ankur ; Hanumolu, Pavan Kumar ; Wei, Gu-Yeon
Author_Institution :
Harvard Univ., Cambridge, MA
Abstract :
This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mismatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; error correction; integrated circuit design; jitter; transceivers; CMOS technology; cascaded-DLL architecture; clock generator phase error correction; delay lock loops; error standard deviation; jitter tolerance bandwidth enhancement; size 0.13 mum; synchronous transceiver; Bandwidth; CMOS technology; Clocks; Error correction; Filtering; Frequency; Jitter; Phase locked loops; Testing; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672120
