Title :
IEEE P1581 - Getting More Board Test Out of Boundary Scan
Author_Institution :
GOEPEL Electron., Austin, TX
Abstract :
IEEE P1581 has undergone significant improvement since its introduction. This paper explains the choice of simple, low overhead solutions the proposed standard provides in overcoming one of boundary scan´s greatest bottlenecks: test of complex memory devices. Design for testability guidelines are provided to allow board designers and test engineers to take full advantage of this new test technique
Keywords :
IEEE standards; boundary scan testing; design for testability; integrated circuit interconnections; integrated memory circuits; IEEE P1581; board test; boundary scan; complex memory devices testing; design for testability; Circuit testing; Clocks; Design engineering; Design for testability; Electronic equipment testing; Guidelines; Pins; Random access memory; Read-write memory; System testing;
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
1-4244-0291-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2006.297707
