• DocumentCode
    3360981
  • Title

    A dynamic offset control technique for comparator design in scaled CMOS technology

  • Author

    Zhu, Xiaolei ; Chen, Yanfei ; Kibune, Masaya ; Tomita, Yasumoto ; Hamada, Takayuki ; Tamura, Hirotaka ; Tsukamoto, Sanroku ; Kuroda, Tadahiro

  • Author_Institution
    Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama
  • fYear
    2008
  • fDate
    21-24 Sept. 2008
  • Firstpage
    495
  • Lastpage
    498
  • Abstract
    A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 times 65 mum2 and consumes 380 muW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.
  • Keywords
    CMOS integrated circuits; comparators (circuits); charge compensation; comparator design; comparator offset control; dynamic offset control technique; power consumption; scaled CMOS technology; timing control; CMOS technology; Capacitors; Circuits; Energy consumption; Inverters; Latches; Preamplifiers; Timing; Virtual colonoscopy; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2018-6
  • Electronic_ISBN
    978-1-4244-2019-3
  • Type

    conf

  • DOI
    10.1109/CICC.2008.4672130
  • Filename
    4672130
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3360981