Title :
DG-JFET for Low Power Applications and Behavior of It as a MOS Capacitor
Author :
Biju, Nitha M. ; Aswathy, M. ; Komaragiri, Rama
Author_Institution :
Dept. of ECE, Nat. Inst. of Technol., Calicut, India
Abstract :
In this work a 22 nm Dual Gate Enhancement Mode Junction Field Effect Transistor (DG-JFET) structure is proposed and its behavior as a MOS capacitor is studied. The results have shown that, the proposed DG-JFET has better short channel effect (SCE) suppression and a lower threshold voltage than MOSFETs. DG-JFETs were recognized as one of the possible choice to continue the scaling beyond the conventional limits. DAVINCI (a Synopsys® 3D-device simulation tool) is used to analyze the device architecture and performance initially. The numerical device simulation results show that the enhancement mode DG-JFETs as an emerging technology to extend the scaling and the parasitic behavior of the device is analyzed from the carrier profile.
Keywords :
MOS capacitors; junction gate field effect transistors; low-power electronics; numerical analysis; DAVINCI; DG-JFET enhancement mode; DG-JFET structure; MOS capacitor; MOSFET; SCE suppression; Synopsys 3D-device simulation tool; dual gate enhancement mode junction field effect transistor; low power applications; low threshold voltage; numerical device simulation; short channel effect suppression; size 22 nm; CMOS integrated circuits; Doping; JFETs; Junctions; Logic gates; MOSFETs; Performance evaluation; SOI JFET; dual gate; low power; n-channel JFET;
Conference_Titel :
Advances in Computing and Communications (ICACC), 2012 International Conference on
Conference_Location :
Cochin, Kerala
Print_ISBN :
978-1-4673-1911-9
DOI :
10.1109/ICACC.2012.30
