Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs

A major challenge to nano-scale CMOS LSIs comprising a large RAM (SRAM or DRAM) block and a logic block is to reduce the minimum operation voltage VDD (Vmin) to the deep-sub-1-V region. However, this is becoming extremely difficult to do in conventional bulk CMOS LSIs as devices and voltages are scaled down. On the contrary, Vmin must be increased, resulting in intolerable increases in power dissipation and internal supply-voltage noise, and degraded device reliability with increase stress voltage. The un-scalable feature of the lowest-necessary VT(VTO) of MOSFETs to keep the subthreshold current low, and the ever-increasing VT variation are responsible for the increase. In particular, the VT variation calls for increasing Vmin to offset increases in speed (delay) variations of circuits, degradation of voltage margins of flip-flops such as SRAM cells and DRAM sense amplifiers, as well as soft-error rate (SER) of RAM cells and even logic gates. Although clarifying and solving the ever-increasing Vmin problem is extremely important and urgent to extend CMOS scaling, to my knowledge, there has been no paper describing the problem systematically and consistently from the view point of circuit designers. This is the case especially for the VT variation issue although it came to light as early as 1994. In this talk, a new evaluation methodology of Vmin is proposed, and the low-voltage-limitation problem and possible solutions for memory-rich deep-sub-100-nm CMOS LSIs are described, putting an emphasis on the VT variation.