Signature Analyzer Design for Yield Learning Support

Signature analyzers are designed to enable identification of failing test response bits directly from failing signatures, without any special diagnosis mode. This ability is useful for yield learning from the large volume of data available from failing chips during production test. The signature analyzers described also tolerate unknown logic values (X´s) and are useful for built-in-self-test and test compression with yield analysis support. Actual defective chip data demonstrates the effectiveness of the presented techniques. Depending on the desired accuracy of failing response bit identification and the number of X´s, test response data is reduced by up to two orders of magnitude