A DSP with caches-a study of the GSM-EFR codec on the TI C6211

Texas Instruments has positioned the C6211 as the low cost member of its C62xx family of DSPs. The C6211 differs from the other devices in this family in that it has a new on-chip memory architecture that uses a two-level cache hierarchy, something not typically seen on a DSP. This paper presents results of a performance study of the TI C6211 running the GSM-EFR speech codec, an important benchmark application in digital cellular telephony. A detailed analysis of the cache performance shows that the caches, although small, are effective in maintaining good performance, even in a multi-programmed workload, where cache pollution affects the memory system performance