An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA

In our previous publication (Cai, et. al., 2005), we demonstrated the ability to generate the proper mix of jitter on ATE to enable the jitter tolerance test for 1.5/3Gbps SATA applications. Obviously this is not the only challenge for performing this test on ATE. Jitter tolerance compliance test for SerDes calls for validation of bit-error-rate (BER) down to the 10^-12 or lower. This requirement deemed this test to be extremely time-consuming, which normally takes more than an hour (assuming running 10¹³ bits for 10^-12 BER level guaranteed). While in the ATE world every test is measured in seconds or even in milliseconds; it is obviously impractical to adopt this test directly. In this paper we demonstrate a new technique to perform the jitter tolerance test >1000 times faster. The technique of course involves extrapolation from the higher BER region down to the 10^-12 level for the compliance test, but the challenge that we faced in getting the extrapolation is very different from the conventional transmitter jitter measurement world. We present a new mathematical model suitable to reason about this extrapolation process