A flexible decoder IC for WiMAX QC-LDPC codes

A programmable and power-efficient decoder IC employing the layered-decoding message-passing algorithm and the low-complexity offset-based Min-Sum check algorithm for irregular QC-LDPC codes is presented. The iterative decoder can be reconfigured to decode all the QC-LDPC codes defined in the Mobile WiMAX standard. Specifically, the decoder achieves a throughput of 68 Mbps at a 100-MHz clock rate for the rate-1/2 length-2304 code with ten iterations, and occupies a core area of 3.4 mm² in 0.18-mum CMOS technology and dissipates estimated 165 mW from a 1.8-V supply. It is 53% smaller, 86% lower in complexity, and has better energy efficiency than other published WiMAX LDPC decoder ASICs, to the best of our knowledge.