DocumentCode :
3361189
Title :
A 3D graphics processor with fast 4D vector inner product units and power aware texture cache
Author :
Yoon, Jae-Sung ; Kim, Lee-Sup ; Yu, Chang-Hyo ; Lee-Sup Kim
Author_Institution :
Dept. of EECS, KAIST, Daejeon
fYear :
2008
fDate :
21-24 Sept. 2008
Firstpage :
539
Lastpage :
542
Abstract :
A 3D graphics system integrating two symmetric unified shader cores for mobile application is presented. To utilize instruction, data, and task level parallelism, a dual-core, dual-issue VLIW and multi-threading method is adopted. For efficient processing, an IEEE-754 compliant fast 4D vector inner product arithmetic unit for matrix multiplication, an internal bus system and a configurable texture cache technique to reduce power consumption in texture unit are proposed. By these methods, the proposed processor achieves 143 Mvertices/s and 2.3 Gtexels/s consuming the power of 367 mW. Also, 45% performance improvement and 26% increase in performance per power ratio are achieved.
Keywords :
cache storage; computer graphic equipment; digital arithmetic; mathematics computing; matrix multiplication; mobile computing; multi-threading; program processors; 3D graphics processor; dual-issue VLIW; fast 4D vector inner product arithmetic units; internal bus system; matrix multiplication; mobile application; multithreading method; power aware texture cache; task level parallelism; unified shader cores; Arithmetic; CMOS technology; Circuits; Energy consumption; Geometry; Graphics; Mobile computing; Parallel processing; Symmetric matrices; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
Type :
conf
DOI :
10.1109/CICC.2008.4672141
Filename :
4672141
Link To Document :
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