Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links

Author

Hong, Dongwoo ; Cheng, Kwang-Ting Tim

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA

fYear

2006

fDate

Oct. 2006

Firstpage

1

Lastpage

10

Abstract

This paper describes a bit error rate (BER) estimation technique for high-speed serial links, which utilizes the jitter spectral information extracted from the transmitted data and some key characteristics of the clock and data recovery (CDR) circuit in the receiver. In addition to improving the accuracy of BER prediction, the estimation technique can be used to accelerate the jitter tolerance test by eliminating the conventional BER measurement process. Experimental results comparing the estimated BER and the BERT-measured BER on a 2.5 Gbps commercial CDR circuit demonstrate the high accuracy of the proposed technique

Keywords

error statistics; estimation theory; integrated circuit testing; jitter; synchronisation; 2.4 Gbit/s; bit error rate estimation; clock and data recovery circuit; high speed serial links; jitter spectral information; jitter testing; Bit error rate; Circuit testing; Clocks; Data mining; Estimation error; Frequency; Jitter; Time measurement; Transfer functions; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2006. ITC '06. IEEE International

Conference_Location

Santa Clara, CA

ISSN

1089-3539

Print_ISBN

1-4244-0292-1

Electronic_ISBN

1089-3539

Type

conf

DOI

10.1109/TEST.2006.297723

Filename

4079401