ESD Immunity Prediction of D Flip-Flop in the ISO 10605 Standard Using a Behavioral Modeling Methodology

Author

Guangyao Shen ; Sen Yang ; Khilkevich, Victor V. ; Pommerenke, David J. ; Aichele, Hermann L. ; Eichel, Dirk R. ; Keller, Christoph

Author_Institution

Electr. & Comput. Eng. Dept., Missouri Univ. of Sci. & Technol., Rolla, MO, USA

Volume

57

Issue

4

fYear

2015

fDate

Aug. 2015

Firstpage

651

Lastpage

659

Abstract

As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18-MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup, including parallel and twisted pair harnesses, is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the failure level with the error of less than 20% in parallel harness case and around 30% in the twisted pair case.

Keywords

electrostatic discharge; flip-flops; twisted pair cables; D flip-flop; ESD immunity prediction; ISO 10605 standard; behavioral modeling methodology; failure prediction accuracy; frequency 18 MHz; integrated circuits; twisted pair case; Clocks; Electrostatic discharges; ISO standards; Integrated circuit modeling; Predictive models; Behavioral model; ISO 10605; flip-flop; parallel harness; twisted pair harness;

fLanguage

English

Journal_Title

Electromagnetic Compatibility, IEEE Transactions on

Publisher

ieee

ISSN

0018-9375

Type

jour

DOI

10.1109/TEMC.2015.2418715

Filename

7089237